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ADuC7060
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit, reduced instruction set computer
(RISC), developed by ARM? Ltd. The ARM7TDMI is a
von Neumann-based architecture, meaning that it uses a single
32-bit bus for instruction and data. The length of the data can
be 8, 16, or 32 bits and the length of the instruction word is
either 16 bits or 32 bits, depending on the mode in which the
core is operating.
The ARM7TDMI is an ARM7 core with four additional
features, as listed in Table 9.
Table 9. ARM7TDMI
debug state. When in a debug state, the processor registers can
be interrogated, as can the Flash/EE, SRAM, and memory
mapped registers.
ARM7 Exceptions
The ARM7 supports five types of exceptions, with a privileged
processing mode associated with each type. The five types of
exceptions are as follows:
Type 1: normal interrupt or IRQ. This is provided to service
general-purpose interrupt handling of internal and external
events. Note, that the ADuC7060 supports eight configurable
Feature
T
D
M
I
Description
Support for the Thumb? (16-bit) instruction set
Support for debug
Enhanced multiplier
Includes the EmbeddedICE? module to support
priority levels for all IRQ sources.
Type 2: fast interrupt or FIQ. This is provided to service data
transfer or a communication channel with low latency. FIQ has
priority over IRQ. Note, that the ADuC7060 supports eight
configurable priority levels for all FIQ sources.
embedded system debugging
THUMB MODE (T)
An ARM instruction is 32 bits long. The ARM7TDMI processor
supports a second instruction set compressed into 16 bits, the
Thumb instruction set. Faster code execution from 16-bit memory
and greater code density is achieved by using the Thumb instruc-
tion set, making the ARM7TDMI core particularly suited for
embedded applications.
However, the Thumb mode has three limitations.
Type 3: memory abort (prefetch and data).
Type 4: attempted execution of an undefined instruction.
Type 5: software interrupts (SWI) instruction that can be used
to make a call to an operating system.
Typically, the programmer defines interrupts as IRQ, but for
higher priority interrupts, the programmer can define
interrupts as the FIQ type.
The priority of these exceptions and vector addresses are listed
?
Relative to ARM, the Thumb code usually requires more
instructions to perform the same task. Therefore, ARM
in Table 10.
Table 10. Exception Priorities and Vector Addresses
code is best for maximizing the performance of time-
Priority
Exception
Address
?
?
critical code in most applications.
The Thumb instruction set does not include some
instructions that are needed for exception handling, so
ARM code can be required for exception handling.
When an interrupt occurs, the core vectors to the interrupt
location in memory and executes the code present at that
address. The first command is required to be in ARM code.
1
2
3
4
5
6
6
Hardware reset
Memory abort (data)
FIQ
IRQ
Memory abort (prefetch)
Software interrupt 1
Undefined instruction 1
0x00
0x10
0x1C
0x18
0x0C
0x08
0x04
MULTIPLIER (M)
1
A software interrupt and an undefined instruction exception have the same
priority and are mutually exclusive.
The ARM7TDMI instruction set includes an enhanced
multiplier, with four extra instructions to perform 32-bit by
32-bit multiplication with a 64-bit result, and 32-bit by 32-bit
multiplication-accumulation (MAC) with a 64-bit result.
EMBEDDED ICE (I)
The EmbeddedICE module provides integrated on-chip debug
support for the ARM7TDMI. The EmbeddedICE module
contains the breakpoint and watchpoint registers that allow
nonintrusive user code debugging. These registers are con-
trolled through the JTAG test port. When a breakpoint or
watchpoint is encountered, the processor halts and enters the
The list of exceptions in Table 10 are located from 0x00 to 0x1C,
with a reserved location at 0x14.
ARM REGISTERS
The ARM7TDMI has 16 standard registers. R0 to R12 are for
data manipulation, R13 is the stack pointer, R14 is the link
register, and R15 is the program counter that indicates the
instruction currently being executed. The link register contains
the address from which the user has branched (when using the
branch and link command) or the command during which an
exception occurred.
Rev. 0 | Page 18 of 100
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